Rosetta: A Realistic Benchmark Suite for Software Programmable FPGAs

Extreme-scale integration of modern system-on-chip (SoC) and escalating design complexity of emerging applications reiterate the importance of designing at a higher level of abstraction and call for an everimproving suite of high-level synthesis (HLS) tools to enable optimization opportunities that are otherwise infeasible at the register-transfer level (RTL) [1]. The need for software programmability is especially pertinent to FPGAs as they emerge from logic devices to computing devices by combining a number of hardened blocks with the programmable fabric [4]. While leveraging the productivity and performance benefits of this new design automation paradigm relies on a line of novel HLS algorithms to exploit the reconfigurability, massive finegrained parallelism, and performance per watt advantage of FPGAs, there lacks a set of benchmarks to provide a practical evaluation of the quality of results (QoR) generated by these algorithms. We present Rosetta: a suite of software applications from a range of domains with hardware constraints targeting heterogeneous FPGAs. Unlike previous efforts, Rosetta provides breath by allowing benchmarking of parametrizable applications beyond the kernel level and incorporates applications from emerging domains. The initial set of applications are implemented in C/C++ and OpenCL to accommodate both the sequential and parallel programming models commonly supported by HLS. Rosetta also emphasizes depth by specifying realistic design constraints for each application. Our multidimensional approach aims to merge research and development among emerging HLS algorithms, software applications, and heterogeneous reconfigurable accelerators.